The relatively low cost of dynamic random access memory (DRAM), as compared to other types of memory such as static random access memory (SRAM) and the like have made it the memory technology of choice for numerous applications including main memory for personal computers, work stations and similar devices, as well as numerous telecommunications devices including network routers, switches, bridges, gateways and the like. The performance of DRAM (e.g., as measured by the amount of time required, on average, for a word or other unit of data to be read from or written to the memory) is typically less favorable than performance available from other memory technologies. One of the factors contributing to the relatively lower performance of DRAM is row access delay. In a typical DRAM, there is a significant delay between the time row access procedures are initiated and the time the first data from the row becomes available for reading-out from the memory. Typically, row accesses include operations such as precharging all columns, addressing a row (or "page"), latching all columns into sense amplifiers and re-driving the columns with the output of the sense amplifiers. Accordingly, it would be advantageous to provide a system in which the effects of row access delays could be reduced so as to improve overall or average DRAM performance.
Many memories are configured to provide relatively rapid access to desired memory locations even when sequentially requested locations are relatively randomly distributed throughout memory. However, there are numerous applications in which many requests are for "bursts" of adjacent column locations within a row (even though the burst may be substantially less than an entire row). One example is when memory is used for storing numerous so-called frames of data in connection with a network switch or router. The design of many memory systems, by focusing on preserving relatively rapid access for randomly-positioned requests, have failed to achieve the type of performance that may be possible when applications typically request memory in bursts. Accordingly, it would be useful to provide a system which exploits the potential presented by particular applications in terms of the typical distribution of memory requests, such as applications in which memory requests are predominantly memory burst requests.
Some memory systems have achieved a degree of performance improvement by organizing the memory in, e.g., two memory banks. In such systems, some performance improvement is achieved by performing certain sequential operations on alternate banks. While it is often feasible to alternate a series of write operations between two banks, it may be infeasible to consistently alternate read operations between two banks. Accordingly, it would be useful to provide a memory system in which performance improvement is substantially consistently available for read operations, write operations or mixtures of the two types of operations.